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Design Verification with E

AUTHOR Palnitkar, Samir
PUBLISHER Prentice Hall (10/05/2003)
PRODUCT TYPE Paperback (Paperback)

Description
An improvement upon Verilog and VHDL, e gives engineers the speed and efficiency to improve the quality of design verification. The text offers examples and exercises as well as a fully functional demo.
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Product Format
Product Details
ISBN-13: 9780131413092
ISBN-10: 0131413090
Binding: Paperback or Softback (Trade Paperback (Us))
Content Language: English
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Page Count: 416
Carton Quantity: 10
Product Dimensions: 7.36 x 1.18 x 9.50 inches
Weight: 2.19 pound(s)
Feature Codes: Bibliography, Index, Price on Product, Illustrated
Country of Origin: US
Subject Information
BISAC Categories
Technology & Engineering | Electrical
Technology & Engineering | Electronics - General
Technology & Engineering | Computer Engineering
Dewey Decimal: 621.392
Library of Congress Control Number: 2003058089
Descriptions, Reviews, Etc.
annotation
As part of the Modern Semiconductor Design series, this book details a broad range of e-based topics including modelling, constraint-driven test generation, functional coverage and assertion checking.
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jacket back

Design Verification with e Samir Palnitkar

Written for both experienced and new users, DesignVerification with e gives you a broadcoverage of e . It stresses the practical verification perspective of e rather than emphasizing only itslanguage aspects.

This book--

  • Introduces you to e-based verification methodologies
  • Describes e syntax in detail, including structs, units, methods, events, temporal expressions. and TCMs
  • Explains the concepts of automatic generation, checking and coverage
  • Discusses the e Reuse Methodology
  • Describes essential topics such as coverage driven verification, e verification components (eVCs), and interfacing with C/C++
  • Illustrates a complete verification example in e
  • Contains a quick-reference guide to the e language
  • Offers many practical verification tips

Includes over 250 illustrations, examples, andexercises, and a verification resource list. Learning objectives and summariesare provided for each chapter.

"Mr. Palnitkar illustrates how and why the power ofthe e verification language and the underlying Specman Elite testbench automationtool are used to develop today's most advanced verification environments. Thisbook is valuable to both the novice and the experienced e user. I highlyrecommend it to anyone exploring functional verification"

--Moshe Gavrielov

Chief Executive Officer

Verisity Design, Inc.

"This book demonstrates how e can be used to createstate-of-the-art verification environments. An ideal book to jumpstarta beginner and a handy reference for experts"

--Rakesh Dodeja

Engineering Manager

Intel Corporation

"The book gives a simple, logical, and well-organizedpresentation of e with plenty of illustrations. This makes it an ideal text book for universitycourses on functional verification"

--Dr. Steven Levitan

Professor

Department of Electrical Engineering

University of Pittsburgh, Pittsburgh, PA

"This book is ideal for readers with little or no e programming experience. It gives the reader athorough and practical understanding of not only the e language, but also how to effectively use thislanguage to develop complex functional verification environments."

--Bill Schubert

Verification Engineer

ST Microelectronics, Inc.

"The flow of the book is logical and gradual. Plentyof illustrations and examples makes this an ideal book for e users. A must-have for both beginners andexperts"

--Karun Menon

Staff Engineer

Sun Microsystems, Inc.

PRENTICEHALL

ProfessionalTechnical Reference

UpperSaddle River, NJ 07458

www.phptr.com

ISBN:0-13-144309-0

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publisher marketing
An improvement upon Verilog and VHDL, e gives engineers the speed and efficiency to improve the quality of design verification. The text offers examples and exercises as well as a fully functional demo.
Show More

Author: Palnitkar, Samir
About the Author

Samir Palnitkar is a recognized authority on Verilog HDL, modeling, verification, logic synthesis, and EDA-based methodologies in digital design. He has worked extensively with design and verification on various successful microprocessor, ASIC, and system projects. He was the lead developer of the Verilog framework for the shared memory, cache coherent, multiprocessor architecture, popularly known as the UltraSPARCTM Port Architecture, defined for Sun's next generation UltraSPARC-based desktop systems. Besides the UltraSPARC CPU, he has worked on a number of diverse design and verification projects at leading companies including Cisco, Philips, Mitsubishi, Motorola, National, Advanced Micro Devices, and Standard Microsystems.

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List Price $94.00
Your Price  $93.06
Paperback