For the last many decades, CMOS technology has played an instrumental role in driving the world economics & scaling down of size has been the fundamental strategy for improving the performance of the device.However, ITRS roadmap suggests that by 2016, the gate length of the MOSFET will be less than 10nm and at these nano scaled regimes both the fundamental limits and technological challenges are going to be encountered.Moreover CMOS technology faces significant challenges like tunneling effect, line edge roughness etc at channel lengths below 45nm. CNT based electronics seems to be a better prospect for extending the saturating Moore's Law because of it's higher mobility, scalability and better channel electrostatics. This book presents an optimum design of a wide bandwidth, high performance CNFET realization of a dual output second generation current conveyor (CCII) at 32nm technology node. The performance of the CCII module has been thoroughly investigated in terms of number of CNT's, the diameter of CNT and inter-CNT pitch.It has been found that CNFET based CCII provides excellent high frequency response along with low power consumption, thus making it a viable proposition for U